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Research Paper | Electronics & Communication Engineering | India | Volume 4 Issue 8, August 2015

Implementation of Image Scaling Algorithm on FPGA

Rahul A. Suryavanshi | Shubha Sheelvant ^[2]

Abstract: In this paper, a low complexity adaptive edge enhanced algorithm is proposed for the implementation of two dimensional (2-D) image scaling applications. The proposed novel algorithm consists of a linear space-variant edge detector, a low complexity sharpening spatial filter and a simplified bilinear interpolation. The edge detector is designed to discover the image edges by a low-cost edge-catching technique. The sharpening spatial filter is added as a pre-filter to reduce the blurring effect produced by the bilinear interpolation. Furthermore, an adaptive technology is used to enhance the effect of the edge detector by adaptively selecting the input pixels of the bilinear interpolation. In addition, an algebraic manipulation and a hardware sharing techniques are used to simplify bilinear interpolation, which efficiently reduces the computing resources and silicon area in VLSI circuits. By adding eight 8-bit registers as a register bank, this design can process streaming data directly and requires only a one-line-buffer memory. The VLSI architecture of this work contains 6.67-K gate counts and achieves about 280-MHz processing rate by using TSMC 0.13-um CMOS process. Compared with the previous low-complexity techniques, this work performs better quality, higher performance, less memory requirements, and lower hardware cost than other image scaling methods.

Keywords: Edge detector, Image zooming, sharpening spatial filter, Two dimensional 2-D Image scalar, and VLSI

Edition: Volume 4 Issue 8, August 2015,

Pages: 441 - 443

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