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M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 4 Issue 9, September 2015
A Low Power Highly Applicable Approach for Caches Based on STT-RAM Technology
Neethu Anna Sabu | Sreeja K. A.
Abstract: The static power dissipation of the peripheral circuits of STT-RAM instruction caches is reduced in this paper. The main goal is to detect the idle time of caches in advance and thereby reduce power consumption. The architecture was further modified to reduce power consumption and to avoid data loss. PEG is introduced along with the architecture. It was applied in ATM and compared with that of conventional RAM. It was implemented and evaluated by XILINX ISE 8.1i and achieved a greater reduction in power.
Keywords: STT-RAM technology, caches, PEG-cache
Edition: Volume 4 Issue 9, September 2015,
Pages: 1325 - 1327
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M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 10, October 2015
Pages: 910 - 914Enhanced Way Tagged Cache Design Using Partial Tag Bloom Filter for Low Level (L2) Cache
Shaima Ibrahim | Sumi Babu
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Case Studies, Electronics & Communication Engineering, India, Volume 4 Issue 6, June 2015
Pages: 1760 - 1767Policy Based an Effective and Efficient Bandwidth Optimisation for Performance Enhancement of an Organisation
Ashok Kumar Tripathi [2] | Ramesh Bharti