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M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 3 Issue 6, June 2014 | Rating: 6.2 / 10
An Efficient VLSI Implementation of Lossless ECG Encoder Design
Vijay Kumar K C | H. S. Veena
Abstract: An efficient VLSI implementation of a lossless electrocardiogram encoding circuit is designed for remote monitoring service. To reduce the wireless transmission power and the amount of storage data; an efficient lossless encoding algorithm had been built for the ECG signal compression. This algorithm consists of an adaptive predictor and a two-stage entropy encoder. The VLSI architecture of this work has the core area of 20308um2 and synthesized by a 180nm CMOS process. It can be operated at 100 MHz processing rate by consuming 1280uW. The data compression ratio is approximately 30.
Keywords: ECG, entropy coding, adaptive predictor, lossless data compression
Edition: Volume 3 Issue 6, June 2014,
Pages: 1458 - 1460