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Informative Article | Computer Engineering | India | Volume 7 Issue 5, May 2018 | Rating: 3.1 / 10
Implement a Digital Speech Encoder, Decoder, Encryption and Decryption on an FPGA
Vishnupriya S Devarajulu [3] | Bharath Ganineni | Sri Prudvi Raj Godthi | Siva Sudhakar Doddapaneni | Mohana Sudha Bandi
Abstract: Increasing need of data protection in computer networks led to the development of several cryptographic algorithms hence sending data securely over a transmission link is critically important in many applications. To achieve higher performance in today?s heavily loaded communication networks, hardware implementation is a wise choice in terms of better speed and reliability. This paper presents the Advanced Encryption Standard (AES) algorithm using Xilinx? virtex7 Field Programmable Gate Array (FPGA). To achieve higher speed and lesser area, Sub Byte operation, Inverse Sub Byte operation, Mix Column operation and Inverse Mix Column operations are designed as Look Up Tables and Read Only Memories. In this paper we presented a description of the components of a speech encoding and how to compress those speech signals. The ISE design suite 14.4 by Xilinx has been used for programming in VHDL for all the blocks of encoder, decoder, encryption and decryption.
Keywords: AES, Rijndael, Cryptography, FPGA, Encryption, Decryption, Encoder, Decoder
Edition: Volume 7 Issue 5, May 2018,
Pages: 1873 - 1877