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Analysis Study Research Paper | Manufacturing Technology | United States of America | Volume 14 Issue 2, February 2025 | Rating: 5.5 / 10
Optimizing Cobalt Integration for <10nm FinFET Technology for Enhanced Middle-of-Line Contact Performance
Sugirtha Krishnamurthy
Abstract: The semiconductor industry's progression to <10nm FinFET technology has significantly increased the demands on middle - of - line (MOL) processes, particularly in contact formation. Traditional tungsten - based contacts encounter challenges, prompting the adoption of cobalt (Co) due to its lower resistivity and superior gap - fill properties. However, integrating cobalt at the gate - bulk (GB) level in 10nm technology introduces compatibility issues with tungsten (W) gates during chemical - mechanical polishing (CMP). Selective amorphous carbon (SAC) cap erosion during GB Cobalt CMP can expose tungsten to corrosive slurries, resulting in gate etchout or void formation key yield detractors in advanced 10nm processes. This paper explores a solution based on a dual titanium nitride (TiN) liner strategy thicker TiN at the trench bottom and a thin (<5?) or no TiN layer at the top combined with a tetramethylammonium hydroxide (TMAH) - based wet recess process selective to tungsten. We present simulated experimental data, illustrated through graphical representations, and contextualize our findings within industry trends and prior studies to assess the viability and potential impact of this strategy on 10nm and future semiconductor manufacturing. Our results, depicted in the graphs, indicate that the dual TiN liner and TMAH recess technique significantly mitigates tungsten gate damage, improves contact resistance, and enhances overall device yield.
Keywords: 10nm FinFET, Cobalt Integration, Middle - of - Line (MOL), Chemical - Mechanical Polishing (CMP), Titanium Nitride (TiN), Tungsten Gate, TMAH Recess, Semiconductor Manufacturing, Contact Resistance, Yield Optimization
Edition: Volume 14 Issue 2, February 2025,
Pages: 1465 - 1467