Rate the Article: Analog VLSI Implementation of Neural Network Architecture, IJSR, Call for Papers, Online Journal
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
Call for Papers | Fully Refereed | Open Access | Double Blind Peer Reviewed

ISSN: 2319-7064

Downloads: 126 | Views: 344

Research Paper | Electronics & Communication Engineering | India | Volume 4 Issue 2, February 2015 | Rating: 6.1 / 10


Analog VLSI Implementation of Neural Network Architecture

Abhishek K. Shrinath


Abstract: Artificial intelligence is realized using artificial neurons. In the proposed design, we are using Artificial neural network to demonstrate the way in which the biological system processes in analog domain. The analog components like Gilbert Cell Multiplier (GCM), Adders, Neuron activation Function (NAF) are used in the implementation. This neural architecture is trained using Back propagation (BP) algorithm in analog domain with new techniques of weight storage. We are using 45nm CMOS technology for layout designing and verification of proposed neural network. The proposed design of neural network will be verified for analog operations like signal amplification and frequency multiplication.


Keywords: Gilbert cell, neuron activation function, neural network, Analog Signals, VLSI


Edition: Volume 4 Issue 2, February 2015,


Pages: 653 - 656



Rate this Article


Select Rating (Lowest: 1, Highest: 10)

5

Your Comments (Only high quality comments will be accepted.)

Characters: 0

Your Full Name:


Your Valid Email Address:


Verification Code will appear in 2 Seconds ... Wait

Top