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M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 4 Issue 7, July 2015 | Rating: 6.2 / 10
High Speed Radix-10 Multiplication Using Redundant BCD Codes
T. Sudha | T. Jyothi
Abstract: In this paper, We propose an algorithm and architecture of a BCD parallel multiplier that exploits some properties of two different redundant BCD codes to speed up its computation. In this paper, we also develop new techniques to reduce the latency and area of previous representative high performance implementations. The Partial products are generated in parallel using a signed-digit radix-10 recoding of BCD multiplier with the digit set [-5, 5], and set of positive multiplicand multiples (0X, 1X, 2X, 3X, 4X, 5X) coded in excess-3 code (XS-3). This encoding has many advantages. First, it is self-complementing codes, so that a negative multiplicand multiple can be obtained by just inverting bits of the corresponding positive one. The available redundancy allows a fast and simple generation of multiplicand multiples in a carry free way. The partial products can be recoded to the overloaded BCD representation (ODDS) by just adding a constant factor into the partial product reduction tree. To show the advantages of our proposed architecture, we have synthesized a RTL model for 16 x 16-digit multiplications and performed a comparative survey of the existing representative designs. We show that the proposed multiplier has an area improvement roughly in the range 20-35 percent for similar target delays with respect to the fastest implementation.
Keywords: Parallel multiplication, decimal hardware, overloaded BCD representation, redundant excess-3 code, redundant arithmetic
Edition: Volume 4 Issue 7, July 2015,
Pages: 2368 - 2373