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M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 5 Issue 7, July 2016

Design Approach towards the High Speed Circular Convolution by using UT Technique and High Speed Parallel Adder

Jamvant Omkar ^[2] | Gurpreet Singh ^[7]

Abstract: Now a days digital devices are going to be a high compact and high portable with high speed designing technique. Digital signal processing and image signal processing is the vast area for researchers and convolution is the best technique for these techniques. In this paper we are designing a high speed convolution technique with low area and high speed. Convolution of the two sequences is the just like as multiplication. Here multiplier is the core element for designing the convolution, like wise adder is the main element+ or device for structuring the multiplier. There are three types of the convolution, Circular, linear and graphical. In this paper we are proposing circular convolution technique by using the Vedic mathematics fast calculation technique. Vedic mathematics is the Ancient Indian Fast calculation method. Modified parallel adder will be used for adding the high bit information. All the analysis and simulation will be done by Xilinx 14.2i software with Spartan 3 Series.

Keywords: Circular Convolution, Linear Convolution, Parallel Adder, Vedic Multiplier VM, UrdhwaTriyakbhayam Sutra UT

Edition: Volume 5 Issue 7, July 2016,

Pages: 778 - 781

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