International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
Call for Papers | Fully Refereed | Open Access | Double Blind Peer Reviewed

ISSN: 2319-7064


Downloads: 117 | Weekly Hits: ⮙1 | Monthly Hits: ⮙1

Research Paper | Electronics & Communication Engineering | India | Volume 8 Issue 11, November 2019


Low Power and Area Efficient Carry Select Adder Using D-Flip Flop

S. Muminthaj | S. Kayalvizhi | K. Sangeetha [4]


Abstract: Area, Power Consumption and Delay are the constituent factors in VLSI design that limits the performance of any circuit. This work presents a simple approach to reduce the area, power consumption and delay of CSLA architecture. Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. Carry Select Adder is efficient for low power application, produces the partial sum and carry by independently generating multiple carries. The proposed design has reduced area, low power consumption when compared to other adders in VLSI. The results analysis shows that the proposed CSLA structure is better than the regular SQRT CSLA.


Keywords: CSLA Adder, RCA, BEC-1, D-FF, Multiplexer


Edition: Volume 8 Issue 11, November 2019,


Pages: 964 - 967


How to Download this Article?

You Need to Register Your Email Address Before You Can Download the Article PDF


How to Cite this Article?

S. Muminthaj, S. Kayalvizhi, K. Sangeetha, "Low Power and Area Efficient Carry Select Adder Using D-Flip Flop", International Journal of Science and Research (IJSR), Volume 8 Issue 11, November 2019, pp. 964-967, https://www.ijsr.net/get_abstract.php?paper_id=ART20202769

Similar Articles with Keyword 'RCA'

Downloads: 140 | Weekly Hits: ⮙1 | Monthly Hits: ⮙1

Research Paper, Electronics & Communication Engineering, India, Volume 2 Issue 5, May 2013

Pages: 229 - 233

Study of R2R 4-Bit and 8-Bit DAC circuit using Multisim Technology

Raghavendra. R | S.A Hariprasad | M.Uttara Kumari

Share this Article

Downloads: 108 | Weekly Hits: ⮙1 | Monthly Hits: ⮙1

Research Proposals or Synopsis, Electronics & Communication Engineering, India, Volume 4 Issue 5, May 2015

Pages: 2277 - 2280

An Improved Feedthrough Logic for Low Power and High Speed Arithmetic Circuits

Avinash Singh [5] | Dr. Subodh Wairya

Share this Article
Top