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M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 4 Issue 12, December 2015

Optimization of FPGA Architecture for Uniform Random Number Generator Using LUT-SR Family

Rita Rawate | M. V. Vyawahare

Abstract: Field-Programmable Gate Arrays (FPGAs) are widely used to implement logic without going through an expensive fabrication process. Field-programmable gate array optimized random number generators (RNGs) are more resource-efficient than software-optimized RNGs because they can take advantage of bitwise operations and FPGA-specific features. The software community has de- veloped a number of high-quality, long period Random Number Generators (RNGs), some of which have been adapted for use in FPGAs. However, these generators were designed to meet the needs of word-level instruction processors, and so are less efficient when mapped to the bit-level operations available in FPGAs. This paper describes a type of FPGA RNG called a LUT-SR RNG, which takes advantage of bitwise XOR operations and the ability to turn lookup tables (LUTs) into shift registers of varying lengths. This provides a good resourcequality balance compared to previous FPGA-optimized generators. This paper deals with optimization of FPGA and simulations is done in VHDL.

Keywords: FPGA Field Programming Gate Array, LUT Look up table, LUT-SR Look up table shift register, Uniform Random Number Geneartor RNG

Edition: Volume 4 Issue 12, December 2015,

Pages: 1804 - 1810

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