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Case Studies | Electronics & Communication Engineering | India | Volume 4 Issue 2, February 2015

Reliable NoC Switch Design with Enhanced Error Handling Capability

Rubina Sabeer | Karthika Manilal ^[2]

Abstract: For systems with intensive parallel communication requirements, buses may not provide the required bandwidth, latency, and power consumption. When the number of computational units integrated onto the same silicon die increases, the communication between the PEs become the major issue. A solution for such a communication bottleneck is the use of an embedded switching network, called Network on Chip (NoC), to interconnect the IP modules in SoCs. NoC relies on data packet exchange. But it may causes fault generation or faulty routing of data packets. The existing techniques for routing of data does not have a capacity to accurately locate faulty components in NoC and distinguish both permanent and tolerable errors. Hence a reliable fault tolerant NoC switch called RKT switch based on adaptive routing module proximity algorithm is used to avoid this problem. A loopback module is placed in each port of the router to avoid data loss or trapping of data inside the routers. The frame work could be modified by using convolution encoding and decoding technique so as to improve the systems fault tolerant behaviour. This system can be implemented on FPGA, which offers the advantages such as high performance, fault tolerance. The coding of each module is simulated and synthesized using the Xilinx ISE Design Suite 13.2 and ModelSim Simulator.

Keywords: SoC, NoC, Loopback, Adaptive XY algorithm, RKT switch, FPGA

Edition: Volume 4 Issue 2, February 2015,

Pages: 1695 - 1700

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