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M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 4 Issue 7, July 2015

Circuit under Test Verification with MSIC Test Pattern Generator

Parvathy Chandra | Vishnu V. S. ^[2]

Abstract: Improvement in quality and reliability are required for digital circuits as their complexity and density increases. Validation of VLSI circuits becomes more difficult with higher test cost. Built-In-Self-Test (BIST) techniques can effectively reduce complexity of VLSI testing, by the introduction of on-chip test hardware into the Circuit Under Test (CUT). In BIST architectures, the Test Pattern Generator (TPG) uses Linear Feedback Shift Register (LFSR) which generates pseudo random patterns that increases the switching activity of test patterns. The test pattern generator generates a multiple single input change (MSIC) vector which increases the accuracy of test response. The Single Input Change (SIC) vector generator uses a reconfigurable Johnson counter to generate minimum transition sequences. The TPG is used in test-per-scan scheme. A combinational circuit is used as the circuit under test, and the output response of CUT is stored in Look Up Table (LUT) for error comparison in LUT method of verification. Reversible technique is also used for the testing the circuit under test. The system is simulated using Xilinx 13.2 design suite.

Keywords: BIST, CUT, LFSR, MSIC

Edition: Volume 4 Issue 7, July 2015,

Pages: 2374 - 2378

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