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Research Paper | Electronics & Communication Engineering | India | Volume 3 Issue 11, November 2014 | Popularity: 6.1 / 10
Ternary Logic Gates and Ternary SRAM Cell Implementation in VLSI
Punnam Nagaraju, Neerati Vishnuvardhan
Abstract: : This paper presents Very Large Scale Integration (VLSI) design and simulation of a ternary logic gates and CMOS ternary SRAM cell. The Simple Ternary Inverter, Positive Ternary Inverter and Negative Ternary Inverter are designed in 180nm technology. The Ternary NAND Gate and Ternary NOR Gate are also designed and simulated. The ternary SRAM consists of crosscoupled ternary inverters. SPICE simulations confirmed that the functional behavior of the READ and WRITE operations is correct
Keywords: Multiple-valued logic MVL, CMOS Ternary Logic, Ternary SRAM, Simple Ternary Inverter STI, Positive Ternary Inverter PTI, Negative Ternary Inverter NTI
Edition: Volume 3 Issue 11, November 2014
Pages: 1920 - 1824