Downloads: 110 | Views: 278
Research Paper | Electronics & Communication Engineering | India | Volume 3 Issue 9, September 2014 | Popularity: 6.7 / 10
Detect and Correct Single Event Upset of the AES Algorithm in On Board Satellite
Md. Riyaj, Vipin Gupta
Abstract: The AES cryptography algorithm can be used to encrypt /decrypt blocks of 128 bits and is capable of using cipher keys of 128, 196 or 256 bits wide (AES 128, AES 196 and AES 256). The AES can be implemented in either software or hardware. The AES is a symmetric key algorithm in which both the sender and the receiver use a single key for encryption & decryption. The encrypted satellite data can get corrupted before reaching the ground station due to various faults. One major source of fault is the harsh radiation environment, Therefore any electronic system used on board satellites such as processors; memories are very susceptible to faults induced by radiation. In this paper we analysis the propagation of faults that occur during transmission due to noise is carried out in order to avoid data corruption and faults are rectified by using hamming Error correction code algorithm. This reduces the data corruption and increases the performances as a result
Keywords: AES, DES, SEU, TWOFISH
Edition: Volume 3 Issue 9, September 2014
Pages: 1062 - 1066
Make Sure to Disable the Pop-Up Blocker of Web Browser
Similar Articles
Downloads: 195 | Weekly Hits: ⮙1 | Monthly Hits: ⮙1
Informative Article, Electronics & Communication Engineering, India, Volume 4 Issue 10, October 2015
Pages: 188 - 191Realization of Smart City Using 5G Cognitive Radio
Lalit Chettri, Syed Sazad
Downloads: 128 | Weekly Hits: ⮙1 | Monthly Hits: ⮙1
Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 3, March 2014
Pages: 108 - 112Design and Simulation of Four Stage Pipelining Architecture Using the Verilog
Rakesh M. R
Downloads: 140 | Weekly Hits: ⮙1 | Monthly Hits: ⮙1
Research Paper, Electronics & Communication Engineering, India, Volume 2 Issue 5, May 2013
Pages: 229 - 233Study of R2R 4-Bit and 8-Bit DAC circuit using Multisim Technology
Raghavendra. R, S.A Hariprasad, M.Uttara Kumari
Downloads: 136
Research Paper, Electronics & Communication Engineering, India, Volume 5 Issue 11, November 2016
Pages: 422 - 426An Segmentation Under Connected Components Based on Watershed Algorithm Using FPGA Processor
R. Kiruthikaa, S. Salaiselvapathy
Downloads: 0
Research Paper, Electronics & Communication Engineering, India, Volume 11 Issue 5, May 2022
Pages: 1837 - 1841Leakage Reduction Technique for Scan Flip-Flop
Nayini Bhavani, Rahul D, Bhavani Kiranmai, J. Yeshwanth Reddy