Downloads: 122 | Views: 218

M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 4 Issue 7, July 2015 | Popularity: 6.3 / 10

Rate This Article!      

Design of Fixed Latency Serial Transceiver on FPGA

Mallika Patil

Abstract: Fixed-latency serial links are essential components of the distributed measurement and control systems. Serial interfaces are generally used for chip-to-chip and board-to-board data transfers. However, largely high-speed Serializer-Deserializer (SerDes) chips do not keep the similar link latency after each power-up or reset, as there is no deterministic phase relationship between the transmitted and received clocks after each power-up. In this project, a fixed-latency serial link based on high-speed transceivers embedded in Xilinx field programmable gate arrays (FPGAs) has been designed. This implementation choice is often made because fixed-latency operations require dedicated circuitry. A fixed-latency serial link is established based on techniques such as dynamic clock phase shifting (DCPS) and changeable delay tuning (CDT). Where a DCPS block utilizes a digital clock manager (DCM) -phase-locked loop (PLL) based clock generator to remove the phase difference between the clock domains in the transmitter and receiver. Our solution can process all possible phase offsets between the transmitted and received clocks, so it relaxes the necessity of fanning in the same reference clock both to the transmitter and to the receiver. We present a specific example of implementation based on the serial transceiver in FPGA.

Keywords: delay tuning, dynamic clock phase shifting, fixed-latency, FPGA, SerDes transceiver

Edition: Volume 4 Issue 7, July 2015

Pages: 482 - 486

Click to Cite this Article

Similar Articles