Downloads: 124 | Views: 229
Research Paper | Electronics & Communication Engineering | India | Volume 4 Issue 7, July 2015 | Popularity: 6.2 / 10
Design of an FFT Processor using Mixed-Radix Algorithm for OFDM system
Jaishri Katekhaye, Amit Lamba
Abstract: A parallel Fast Fourier Transform (FFT) processor for the use in Orthogonal Frequency Division Multiplexing (OFDM) is proposed here. The proposed processor is 64-point which is based on mixed radix (4-2) algorithm and execute 16-bit fixed point data format. The clock cycles required for the FFT processor are 92 which are less in number due to the use of parallel processing. The delay required for simulation of 64-point FFT is 11.924ns. For simulation we used XILINX 14.2 ISE software and for coding we employed Very High Speed Integrated Circuit Hardware Description Language (VHDL).
Keywords: FFT, Mixed Radix, OFDM, VHDL
Edition: Volume 4 Issue 7, July 2015
Pages: 415 - 419
Similar Articles
Downloads: 136
Research Paper, Electronics & Communication Engineering, India, Volume 5 Issue 11, November 2016
Pages: 422 - 426An Segmentation Under Connected Components Based on Watershed Algorithm Using FPGA Processor
R. Kiruthikaa, S. Salaiselvapathy
Downloads: 1
Research Paper, Electronics & Communication Engineering, Egypt, Volume 10 Issue 12, December 2021
Pages: 1281 - 1287Feature Level Fusion of Palmprint and Iris Images for Person Identification
May Essam, Fayez Wanis Zaki, Mervat El-Seddek
Downloads: 2 | Weekly Hits: ⮙2 | Monthly Hits: ⮙2
Masters Thesis, Electronics & Communication Engineering, India, Volume 11 Issue 7, July 2022
Pages: 575 - 578An FPGA-Based Implementation of Emotion Recognition Using EEG Signals
Sonia Stanley Louis, Dr. Mahantesh K.
Downloads: 103
M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 5, May 2015
Pages: 3221 - 3230Implementation of RSA Cryptosystem Using Ancient Indian Vedic Mathematics
Shahina M. Salim, Sonal A. Lakhotiya
Downloads: 103
Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 7, July 2015
Pages: 2468 - 2472VHDL Implementation for Adaptive FIR filter and its Novel Application using Systolic Architecture
Ghanshyam A. Chune, Vijay Bagdi