International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
Call for Papers | Fully Refereed | Open Access | Double Blind Peer Reviewed

ISSN: 2319-7064


Downloads: 127 | Views: 292

Research Paper | Computer Science & Engineering | India | Volume 4 Issue 3, March 2015 | Popularity: 6.1 / 10


     

An Efficient Buffer less Rank Based Fault Tolerance Network on Chip System

Subodh Kakran


Abstract: Network-on-chip (NoC) designs are based on a compromise among the most important elements viz. power dissipation, latency and the balance is usually defined at design time. In the research work we have used Efficient Rank Based fault-tolerant deflection routing (FTDR) algorithm to tolerate faults. The research is intended to reduce the router area by avoiding the table based routing path computation. The Efficient Rank Based algorithm has been proposed in the research to reduce the area and the power consumption of the overall Network on Chip. For Rank-Based fault tolerant deflection routing we provide a particular rank to our routers according to our NoC routing path (s). It does not require routing table to update completed path and switching path.


Keywords: NoC, FTDR, Rank Based Algorithm, FTDR-H, Fault Tolerance NoC


Edition: Volume 4 Issue 3, March 2015


Pages: 190 - 192



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Subodh Kakran, "An Efficient Buffer less Rank Based Fault Tolerance Network on Chip System", International Journal of Science and Research (IJSR), Volume 4 Issue 3, March 2015, pp. 190-192, https://www.ijsr.net/getabstract.php?paperid=SUB158115, DOI: https://www.doi.org/10.21275/SUB158115




Downloads: 127 | Views: 292

Research Paper | Biology | India | Volume 4 Issue 9, September 2015 | Popularity: 6.1 / 10


     

An Efficient Buffer less Rank Based Fault Tolerance Network on Chip System

Subodh Kakran


Abstract: Network-on-chip (NoC) designs are based on a compromise among the most important elements viz. power dissipation, latency and the balance is usually defined at design time. In the research work we have used Efficient Rank Based fault-tolerant deflection routing (FTDR) algorithm to tolerate faults. The research is intended to reduce the router area by avoiding the table based routing path computation. The Efficient Rank Based algorithm has been proposed in the research to reduce the area and the power consumption of the overall Network on Chip. For Rank-Based fault tolerant deflection routing we provide a particular rank to our routers according to our NoC routing path (s). It does not require routing table to update completed path and switching path.


Keywords: NoC, FTDR, Rank Based Algorithm, FTDR-H, Fault Tolerance NoC


Edition: Volume 4 Issue 9, September 2015


Pages: 863 - 866



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Text copied to Clipboard!
Subodh Kakran, "An Efficient Buffer less Rank Based Fault Tolerance Network on Chip System", International Journal of Science and Research (IJSR), Volume 4 Issue 9, September 2015, pp. 863-866, https://www.ijsr.net/getabstract.php?paperid=SUB158115, DOI: https://www.doi.org/10.21275/SUB158115



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