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Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 7, July 2015
2387 - 2390Design of Wallace Tree Multiplier using Adiabatic Logic
Bhushan V. Mude | Prof. R. N. Mandavgane [2] | Prof. A. P. Bagde
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M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 6, June 2015
2737 - 2741A Hierarchical Design of High Performance Carry Select Adder Using Reversible Logic
Amol D. Rewatkar | R. N. Mandavgane [3] | S. R. Vaidya [2]
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M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 6, June 2015
1843 - 1847Design of 8 x 8 Vedic Multiplier using Quaternary-Logic & Pipelining Architecture
Vivek D. Wanjari | Prof. R. N. Mandavgane [2] | Prof. Shailesh Sakhare
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