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M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 3 Issue 9, September 2014
563 - 567VLSI Implementation of Parallel Prefix Subtractor using Modified 2's Complement Technique and BIST Verification using LFSR Technique
Malti Kumari | Vipin Gupta [2] | Gaurav K Jindal
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Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 9, September 2014
1062 - 1066Detect and Correct Single Event Upset of the AES Algorithm in On Board Satellite
Md. Riyaj | Vipin Gupta [2]
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