Performance Evaluation of CNTFET Based Ternary Basic Gates and Half Adder

Gaurav Agarwal, Amit Kumar

Abstract: The shrinkage in size of VLSI chips as well as improved energy efficiency is the need of the modern digital era. Using ternary logic instead of conventional binary logic helps to reduce circuit complexity and hence reduces chip area. Carbon nanotubes FET (CNTFET) are preferred over CMOS for logic design due to its high performance i. e. excellent transport property, low resistivity and higher current on-off ratio. The performance of ternary based logic gates is evaluated in terms of parameter such as power dissipation and delay.

Keywords: Carbon nanotube CNT, Single walled CNT SWCNT, Multiple valued logic MVL, Carbon nanotube FET CNTFET

How to Cite?: Gaurav Agarwal, Amit Kumar, "Performance Evaluation of CNTFET Based Ternary Basic Gates and Half Adder", Volume 5 Issue 5, May 2016, International Journal of Science and Research (IJSR), Pages: 787-791, https://www.ijsr.net/getabstract.php?paperid=10051601, DOI: https://dx.doi.org/10.21275/10051601

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