Downloads: 140
Research Paper | Electronics Communication Engineering | Volume 2 Issue 9, September 2013 | Pages: 80 - 83 | India
Design and Analysis of Low Power Implicit Pulse Triggered Flip-Flops
Abstract: In this paper, a novel low-power pulse-triggered flip-flop (P-FF) design is presented. Pulse- triggered FF (P-FF) has been considered as a popular alternative to the conventional master slave based FF in the applications of high speed. In particular, digital designs now-a-days often adopt intensive pipelining techniques and employ many FF-rich Modules. It is also estimated that the power consumption of the clock system, which consists of clock distribution networks and storage elements, is as high as 20 %45 % of the total system power. First, the pulse generation control logic, an AND function, is removed from the critical path to facilitate a faster discharge operation. A simple two-transistor AND gate design is used to reduce the circuit complexity. Second, a conditional pulse-enhancement technique is devised to speed up the discharge along the critical path only when needed. As a result, transistor sizes in delay inverter and pulse-generation circuit can be reduced for power saving. The simulations are done using Microwind & DSCH analysis software tools. Our proposed system simulations are done under 50nm technology and the results are compared with other conventional flip-flops. Hence, our proposed system is showing better output than the other flip-flops.
Keywords: DSCH, Flip-Flop, low power, Microwind, Pulse triggered
How to Cite?: K. Lovaraju, K. Rajendra Prasad, "Design and Analysis of Low Power Implicit Pulse Triggered Flip-Flops", Volume 2 Issue 9, September 2013, International Journal of Science and Research (IJSR), Pages: 80-83, https://www.ijsr.net/getabstract.php?paperid=31081303, DOI: https://dx.doi.org/10.21275/31081303