Comparative Analysis of a Low Power and High Speed Hybrid 1-Bit Full Adder for ULSI Circuits

K. Mariya Priyadarshini, M. Naga Sabari

Abstract: Full adder circuit is a basic building block for designing any arithmetic circuits. Due to high demands and need for low and high speed digital circuits with small silicon area scaling trends have increased tremendously. In this paper a new high speed full adder circuit is proposed with very less static and dynamic power dissipation which occupies less silicon area when compared with existing techniques. For 1.8-V supply at 180m technology the average power consumption (0.306mw) was found to be extremely low with a delay of 728.54ps. Correspondingly values of the same are found to be 0.034mw and 44.235ps with 1.2V supply at 130nm technology. The design was further extended for implementing 32-bit full adder and is found to be efficiently working with only 23.3088ns (1.41552ns) delay and 9.792mw (1.088mw) power at 180m (130nm) technology for 1.8V (1.2V) supply voltage. In comparison with the existing full adder designs the proposed circuit offers significant improvement in terms of area, speed and power.

Keywords: carry propagation, gate diffusion, high speed, low power, logic styles