International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
Call for Papers | Fully Refereed | Open Access | Double Blind Peer Reviewed

ISSN: 2319-7064


Downloads: 140 | Views: 485 | Weekly Hits: ⮙1 | Monthly Hits: ⮙1

Research Paper | Electronics & Communication Engineering | India | Volume 2 Issue 5, May 2013 | Popularity: 6.5 / 10


     

Study of R2R 4-Bit and 8-Bit DAC circuit using Multisim Technology

Raghavendra. R, S.A Hariprasad, M.Uttara Kumari


Abstract: An R-2R Ladder is a simple and inexpensive way to perform digital to analog conversion, using repetitive arrangements of precision resistor networks in a ladder-like configuration. The application of Multisim for realizing R2R DAC bridges the gap between theory and the real circuits. This paper provides a detailed view of a 4 bit and an 8 bit R2R ladder with optimum accuracy by using Multisim. Experiments are performed on 4 bit and 8 bit R2R ladder with decade counter (staircase) and the accuracy of Theoretically experimented and Multisim experimented scenarios are compared. The comparison shows higher range of accuracy is obtained when R2R ladder is experimented in Multisim, Multisim offers additional features such as ease of implementation rebuild and cost reduction when compared to practical simulation of R2R ladder.


Keywords: R2R Ladder, DAC, Staircase, Multisim, Counter


Edition: Volume 2 Issue 5, May 2013


Pages: 229 - 233



Make Sure to Disable the Pop-Up Blocker of Web Browser




Text copied to Clipboard!
Raghavendra. R, S.A Hariprasad, M.Uttara Kumari, "Study of R2R 4-Bit and 8-Bit DAC circuit using Multisim Technology", International Journal of Science and Research (IJSR), Volume 2 Issue 5, May 2013, pp. 229-233, https://www.ijsr.net/getabstract.php?paperid=IJSRON1201354, DOI: https://www.doi.org/10.21275/IJSRON1201354



Click below to Watch Video Lecture of Above Article

ePresentation

Share this Video Lecture

Similar Articles

Downloads: 2 | Weekly Hits: ⮙2 | Monthly Hits: ⮙2

Analysis Study Research Paper, Electronics & Communication Engineering, India, Volume 11 Issue 11, November 2022

Pages: 966 - 969

High Speed Low Power 8-Bit Binary up Counter in 45nm CMOS Technology

S. Sivashankari

Share this Article

Downloads: 4 | Weekly Hits: ⮙1 | Monthly Hits: ⮙1

Doctoral Thesis, Electronics & Communication Engineering, India, Volume 12 Issue 10, October 2023

Pages: 1837 - 1843

Minimization of Energy Hole in Under Water Sensor Networks (UWSNs)

Anurag Kumar, Dr. Arvind Kumar, Dr. Sanjat Kumar Mishra

Share this Article

Downloads: 11 | Weekly Hits: ⮙1 | Monthly Hits: ⮙2

Research Paper, Electronics & Communication Engineering, India, Volume 13 Issue 2, February 2024

Pages: 179 - 185

Drone Detection using Multi-Sensor Data Fusion

Praveen Kumar S, Dr. Rajanikanth Kashi Nagaraj

Share this Article

Downloads: 101 | Weekly Hits: ⮙1 | Monthly Hits: ⮙1

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 6, June 2015

Pages: 2835 - 2838

Efficient Implementation of Digital Receiver on FPGA

M. Sravani, B. Madhavi

Share this Article

Downloads: 107

Review Papers, Electronics & Communication Engineering, India, Volume 4 Issue 1, January 2015

Pages: 975 - 978

A Review on PAPR Reduction Technique in OFDM

Kiran Kumari, Hemant Dhabhai

Share this Article



Top