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Research Paper | Electronics & Telecommunication Engineering | India | Volume 2 Issue 2, February 2013 | Rating: 6.6 / 10

FPGA Implementation of Codec Design for Optimal Code Rate Crosstalk Avoidance Codes

K. Ramesh ^[9] | E. Srinivas ^[3]

Abstract: In deep submicron (DSM) technology, the coupling capacitance is comparable to or exceeds the self or substrate capacitance, which in turn causes the delay of a transition in a wire to be twice or more than that of a wire transitioning next to a steady signal. In this paper, the authors propose a new coding technique which minimizes both coupling and self transition activities in the bus lines using the CODEC design of all classes of CACs based on binary mixed-radix numeral systems and spatial redundancy respectively. Using this framework, we then propose novel CODEC designs for three important classes of CACs; one lambda codes (OLCs), FPCs, and forbidden overlapping codes (FOCs). Our CODEC designs have area complexity and delay that increase quadratically with the size of the bus, while achieving optimal or nearly optimal code rates. Using an FPGA kit we can observe the CACs results on it.

Keywords: CODEC, crosstalk avoidance codes (CACs), interconnect, numeral systems, FPGA kit

Edition: Volume 2 Issue 2, February 2013,

Pages: 614 - 622