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M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 4 Issue 11, November 2015 | Rating: 6.4 / 10
Area Optimized Double Precision IEEE Floating Point Adder
Elizabeth Joseph Mattam | Deepa Balakrishnan
Abstract: The fields of science, engineering and finance require manipulating real numbers efficiently. Since the first computers appeared, many different ways of approximation real numbers on it have been introduced. One of them, the floating point arithmetic, is the most efficient way of representing real numbers in computers. Representing an infinite, continuous set of (real numbers) with a finite set of (machine numbers) is not an easy task some compromises must be found between speed, accuracy and efficient use and also implementation and memory cost. Floating Point Arithmetic represent a very good compromise for numerical applications. Floating Point (FP) addition, subtraction and multiplication are widely used in large set of scientific and signal processing computation. Although the concept of Floating-Point addition is easy it imposes a immense challenge while implementation of complex algorithm in hard real-time due to the enormous computational burden with repeated calculations with high precision numbers. A novel technique to implement a double precision IEEE floating-point adder which can complete the operation within two clock cycles. The proposed technique has exhibited improvement the operational chip area management by modifying the carry select adder. Also a decrease in power is also expected since area and power are directly proportional.
Keywords: Area optimized carry select adder, Floating point adder, area and power reduction, CSLA, Clock cycles
Edition: Volume 4 Issue 11, November 2015,
Pages: 344 - 347