Design and Implementation of 8 BIT Vedic Multipliers USING HNG Gates

Illa Bharti, Manisha Waje

Abstract: Now a days, reversible logics are emerging field in VLSI design in which Energy dissipation is an important consideration. Reversible logic is first related to energy. Researcher like Landauer states that information loss due to function irreversibility leads to energy dissipation. Thus reversibility will become an essential feature in future electronics circuit design. Reversible circuits are of high interest in applications like DSPs, low power CMOS design, nanotechnology, optical computing and quantum computing etc. The main aim and purpose of this paper is to improve the speed and power dissipation of the processor by using efficient Vedic multiplier. Vedic multiplier known as Urdhva Tiryakbhayam which means vertical and crosswise in English. This multiplier is designed and implemented using reversible logic Feynman Gate, Peres Gate and HNG gate. Feynman and Peres gates are used to implement the basic two bit multipliers and HNG gate is used as full adder for summation of the partial product generated by two bit multipliers in four bit multiplier.8*8 bit multiplier is designed using four bit multipliers and three eight bit ripple carry adders. The proposed system is designed using VHDL and implemented through Xilinx ISE 13.2 Navigator

Keywords: Vedic multiplier, Urdhva Tiryakbhayam, Reversible logic gates, Garbage outputs, Constant outputs, Xilinx Sparta 3E FPGA kit