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Research Paper | Electronics & Communication Engineering | India | Volume 9 Issue 5, May 2020 | Popularity: 6.4 / 10
Implementing of 16-Bit Pyramidal Adder for Arithmetic Applications
Thokala Mohan Rao
Abstract: Adders plays vital role in DSPprocessing applications and FPGA based VLSI environment where power, delay, speed and area are important parameters, so we need to reduce all parameter values as possible as possible. In all arithmeticoperations power, delay, speed  and area  all  are  important and depend on multiplier which in turn depends on adders. So if we modify the adders namely half adder and full adder we can reduce parameter values. By implementing nomal half adder and full adder we can reduce the delay.
Keywords: multiplexer MUX, half adder HA, full adder FA, field programmble gate aray FPGA, digital signal processing DSP
Edition: Volume 9 Issue 5, May 2020
Pages: 686 - 688
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