High Speed Low Power 8-Bit Binary up Counter in 45nm CMOS Technology

S. Sivashankari

Abstract: This article presents the schematic design of a new 8-bit binary counter. The 8-bit binary counter is designed to achieve lower power consumption with high-speed operation. Circuit level simulations are done to check the circuit functionality and the layout is made by connecting the components manually. At last, the layout is simulated to know whether the output signal is affected by parasitic resistance and capacitance. Test structures of the Counter are designed using 45 nm Technology with Tanner EDA environment. Thus, the proposed circuit is designed and implemented to overcome these limitations.

Keywords: Power dissipation, lower offset voltage, binary up counter, Tanner EDA tool