Downloads: 0 | Views: 41
Informative Article | Electrical Engineering | India | Volume 10 Issue 10, October 2021 | Rating: 4.6 / 10
Impact of Low Dynamic Logic Power SoCs on Energy Optimizing Techniques
Apoorva Reddy Proddutoori
Abstract: Larger capacitive loads procure the need for high - speed dynamic logic design implementations leading to higher power consumption. In search of new dynamic gate logic has been of utter importance for design and power optimization. One of the most useful utilizing has been observed through inductor - capacitor (LC) resonation reducing the switching power drastically, by transferring the energy to inductor during operations. This gate, implemented in a CMOS process, demonstrates on - chip integration feasibility with low dynamic power consumption. Collaboration across disciplines is essential for evolving device co - design and low - power technology in SoCs. Designing low - power mobile SoCs involves hardware development, integrated signal devices, circuits, and nanoscale CMOS technology. Reducing power consumption in low - voltage circuits is critical to minimize leakage in active and standby modes. Circuit layout and physical design techniques should be utilized to achieve current reduction. The paper discusses circuit techniques, physical design, voltage island technology, custom design methods, power management, and silicon implementation platform design for efficient SoCs.
Keywords: switching power, energy, leakage, gate logic, inductor - capacitor resonance, System - on - chips (SOCs)
Edition: Volume 10 Issue 10, October 2021,
Pages: 1607 - 1609