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Research Paper | Electronics & Communication Engineering | India | Volume 4 Issue 3, March 2015 | Rating: 6.3 / 10
Design and Optimization of LDO Regulator with MTCMOS Techniques
S. Bharathi [3] | M. C. Sathiya [2]
Abstract: Advances in VLSI technology changed that to allow the creation of System-on-Chip (SoC) devices that integrated those discrete components on a single chip. The most obvious driver for low-power environments leads to increase the demand for battery operated application. Highly accurate Low Drop-Out (LDO) regulators in power supply ICs are typically under 500mA, and frequently used in a wide range of electronic products. LDOs provide a power management solution and satisfying their needs like low power, space-conscious design etc. The main characteristic of the LDO regulator design is to minimize the quiescent current and dropout voltage so as to provide high efficiency. The proposed LDO regulator uses ultra-low quiescent class-AB error amplifier (ERR AMP) and a slew-rate (SR) enhancement circuit to minimize the effect of capacitance and speed up transient response designed in the 180nm technology. The MTCMOS design technique is used to reduce the quiescent current than conventional LDO. It increased the demand for low-cost energy-constrained system applications. The proposed LDO design is simulated by using the cadence analog environment.
Keywords: Power supply IC, Class- AB error amplifier, Low-dropout regulator, Slew rate
Edition: Volume 4 Issue 3, March 2015,
Pages: 362 - 366