Design of High Speed VLSI Architecturefor 1-D Discrete Wavelet Transform

Rashmi Patil, Dr. M. T. Kolte

Abstract: The work presents an implementation of discrete wavelet transform (DWT) using systolic array architecture in VLSI. The architecture consists of filter unit, storage unit and control unit. This performs calculations of low pass and high pass coefficients by using only one multiplier. This architecture has been implemented and simulated using VLSI. The hardware utilization efficiency is more as compared to the referred due to the FBRA scheme. The systolic nature of this architecture corresponds to a clock speed of 19.27MHz for Coiflets1 wavelet as compared to other two wavelets. It has advantage for optimizing area and time. The architecture is modular and cascadable for one or multi-dimensional DWT.

Keywords: DWT, FRA, hardware efficiency, six tap Fir Filter, Systolic Array