Downloads: 111 | Views: 307
Research Paper | Electronics & Communication Engineering | India | Volume 4 Issue 6, June 2015 | Popularity: 6.4 / 10
Wide Range Enable Level Shifter for Multi-Supply Voltage Designs
Puneet Patil, D Sheshachalam
Abstract: In the current SoC design methodologies, the multi supply voltage and power gating techniques are used widely which require special cells in design. A new enable level shifter is designed which comprises the function of level shifter and isolation cell. The voltage level shifting is achieved by the use of modified Wilson current mirror circuits, which gives wide range of input voltage. In the given ELS, the output will be clamped to ground when the enable signal is high i. e. during the power domain shut down. This avoids the false triggering of transistors in the subsequent blocks. The proposed ELS is designed using SPICE model of 32nm technology and simulated. The ELS can reliably convert 100mV input voltage to 0.9V, with the delay of 5ns. The power consumption of the cell is 100nW at 0.9V input voltage.
Keywords: multi voltage supply design, dynamic voltage scaling, power gating, isolation cells, modified Wilson current mirror, ELS, SPICE
Edition: Volume 4 Issue 6, June 2015
Pages: 987 - 991
Make Sure to Disable the Pop-Up Blocker of Web Browser
Similar Articles
Downloads: 2 | Weekly Hits: ⮙2 | Monthly Hits: ⮙2
Research Paper, Electronics & Communication Engineering, India, Volume 13 Issue 8, August 2024
Pages: 1821 - 1823Power Efficient Voltage Level Shifter using RCC Network and Stacking Technique
Rentala Laxmi Sindhuja
Downloads: 4 | Weekly Hits: ⮙1 | Monthly Hits: ⮙2
Research Paper, Electronics & Communication Engineering, India, Volume 10 Issue 6, June 2021
Pages: 1505 - 1508Design of Two Stage CMOS Operational Amplifier
Rahul Kumar
Downloads: 105
M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 6, June 2015
Pages: 1843 - 1847Design of 8 x 8 Vedic Multiplier using Quaternary-Logic & Pipelining Architecture
Vivek D. Wanjari, Prof. R. N. Mandavgane, Prof. Shailesh Sakhare
Downloads: 106
Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 12, December 2015
Pages: 2270 - 2274Design and Simulation of NOT and NAND Gate Using Hybrid SET-MOS Technology
Daya Nand Gupta, S. R. P. Sinha
Downloads: 107
Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 9, September 2014
Pages: 943 - 949Design and Analysis of CMOS Multipliers at 180nm and 350nm
Jagmeet Singh, Hardeep Singh