Sum to Modified Booth Recoding Techniques for Efficient Design of the Fused Add-Multiply Operator

D.S. Vanaja, S. Sandeep

Abstract: Digital Signal Processing (DSP) applications carry out a large number of complex arithmetic operations. Multiplier plays an important role in high performance of the system, reduce the power and area. In this paper we focus on optimizing the design of Fused Add Multiply (FAM) operator for increasing performance. We introduce new techniques to implement the direct recoding of the sum of two numbers in its Modified Booth (MB) form. We propose a structured and efficient recoding technique and explore three different schemes by incorporating them in Fused Add Multiply (FAM) designs. Comparing the proposed FAM designs with existing recoding schemes, the proposed technique gives considerable reductions in terms of critical delay, power consumption and hardware complexity of the FAM unit.

Keywords: Add-Multiply operation, Arithmetic circuits, Modified Booth recoding, VLSI design